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Analog Digital ASICs design_Part II
大小 1000.57 MB
文件数 146
Info Hash: EF0FAD788064A2CCCE7BD9FE24D7B3BC6432D0A9
收录时间 2025-12-21 14:55:36
更新时间 2025-12-21 14:55:36
文件列表 (146)
Articles about Design Verification Techniques/A Case Study of Verification with Embedded Checkers.pdf
302.41 KB
Articles about Design Verification Techniques/A Recipe for Multi-Million Gate ASIC Verification.pdf
69.73 KB
Articles about Design Verification Techniques/A Strategic Process for System Level Verification.pdf
564.04 KB
Articles about Design Verification Techniques/Assertion Monitor Library_100.pdf
154.06 KB
Articles about Design Verification Techniques/Component Verification by Example.pdf
160.47 KB
Articles about Design Verification Techniques/Design and Verification IP for PCI and PCI-X.pdf
324.46 KB
Articles about Design Verification Techniques/Exploiting the Power of Vera--Creating Useful Class Librarie.pdf
105.82 KB
Articles about Design Verification Techniques/Functional Verification of a HW Block Using VERA.pdf
71.02 KB
Articles about Design Verification Techniques/Functional Verification with Embedded Checkers --Paper.pdf
176.95 KB
Articles about Design Verification Techniques/Getting It Right--AMS Design and Verification Strategies.pdf
228.81 KB
Articles about Design Verification Techniques/High Level Data Structures in Verification and Behavioral Mo.pdf
1.05 MB
Articles about Design Verification Techniques/Portable Automatic In-Situ Testbench Generation-- A Case Stu.pdf
140.67 KB
Articles about Design Verification Techniques/practical_soc_verification.pdf
100.92 KB
Articles about Design Verification Techniques/Random Generation Tutorial.pdf
1.53 MB
Articles about Design Verification Techniques/Shotgun E An Eight-Step Approach to Experience Random Verifi.pdf
133.65 KB
Articles about Design Verification Techniques/Spec-Based Verification.pdf
129.6 KB
Articles about Design Verification Techniques/The Case for eVCs.pdf
124.64 KB
Articles about Design Verification Techniques/The Five-Day Verification Plan.pdf
73.18 KB
Articles about Design Verification Techniques/Using VCS with White-Box Verification Techniques --Paper.pdf
36.49 KB
Articles about Design Verification Techniques/Using VERA to Test a DMA Engine.pdf
41.22 KB
Articles about Design Verification Techniques/Vera, Vera On the Wall, Useful Lessons for First-Time Vera U.pdf
81.62 KB
Articles about Design Verification Techniques/Verification Methodology of Multi-Million Gate Networking So.pdf
47.61 KB
Articles about Design Verification Techniques/Verifying Virtual Components and VC-Based SoC Designs --pape.pdf
311.24 KB
Articles about Design Verification Techniques/When Test Vectors are Useless -- Verifying IP-Based SOC Desi.pdf
538.44 KB
Articles about Design Verification Techniques/White-Box Verification for Complex Designs.pdf
95.75 KB
CMOS Circuit Design, Layout, and Simulation.R.Jacob Baker, Harry W.Li, David E.Boyce.pdf
149.94 MB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/appendixa.pdf
287.89 KB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/appendixb.pdf
516.49 KB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/appendixc.pdf
252.07 KB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/appendixd.pdf
373.27 KB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/appendixe.pdf
185.13 KB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/appendixf.pdf
262.7 KB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch0.pdf
172.94 KB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch1.pdf
688.1 KB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch10.pdf
1.4 MB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch11.pdf
1.04 MB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch12.pdf
1.31 MB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch13.pdf
787.73 KB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch14.pdf
1.55 MB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch15.pdf
335.52 KB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch16.pdf
146.14 KB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch2.pdf
684.41 KB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch3.pdf
849.81 KB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch4.pdf
762.8 KB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch5.pdf
1.1 MB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch6.pdf
964.48 KB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch7.pdf
807.1 KB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch8.pdf
636.82 KB
Deep-submicron CMOS circuit design.Simulator in hands.Etienne Sicard,Sonia Delmas Bendhia/bookch9.pdf
438.05 KB
Delta-Sigma Data Converters. Theorym Design and simulation.S.R.Norwosrthy, R.Schreier, G.C.Temes/ds1.pdf
4.27 MB
Delta-Sigma Data Converters. Theorym Design and simulation.S.R.Norwosrthy, R.Schreier, G.C.Temes/ds2.pdf
4.06 MB
Delta-Sigma Data Converters. Theorym Design and simulation.S.R.Norwosrthy, R.Schreier, G.C.Temes/ds3.pdf
4.27 MB
Delta-Sigma Data Converters. Theorym Design and simulation.S.R.Norwosrthy, R.Schreier, G.C.Temes/ds4.pdf
3.99 MB
Delta-Sigma Data Converters. Theorym Design and simulation.S.R.Norwosrthy, R.Schreier, G.C.Temes/ds5.pdf
3.97 MB
Delta-Sigma Data Converters. Theorym Design and simulation.S.R.Norwosrthy, R.Schreier, G.C.Temes/ds6.pdf
4.38 MB
Delta-Sigma Data Converters. Theorym Design and simulation.S.R.Norwosrthy, R.Schreier, G.C.Temes/ds7.pdf
4.34 MB
Design of Analog CMOS Integrated Cirquits.Behzad Razavi/cmos errata.pdf
19.11 KB
Design of Analog CMOS Integrated Cirquits.Behzad Razavi/Design of Analog CMOS Integrated Circuits.pdf
17.32 MB
Design of analog Integrated Cirquits and Systems.Kenneth.R.Laker,Willy.M.C.Sansen.pdf
204.01 MB
Design of Low-voltage Low-Power CMOS Delta-Sigma AD Converters.Vincento Peluso,Michel Steyaert,Willy Sansen.pdf
18.97 MB
Design of Low-Voltage Low-Power Operational Amplifiers Cells.Ron Hogervorst,Johan H.Huijsing.pdf
33.86 MB
Design of System on a Chip.Devices & Components.Ricardo Reis, Jochen A.G. Jess.pdf
7.04 MB
Designing Analog Chips.Hans Camenzind.pdf
1.92 MB
Designing with Operational amplifiers.Applications Alternatives.Jerald G.Graeme.pdf
9.11 MB
ECE422_ECE522 CMOS IC Technologies Lectures. Karti Mayaram/hand-all.pdf
7.53 MB
ECE422_ECE522 CMOS IC Technologies Lectures. Karti Mayaram/part1.pdf
1.04 MB
ECE422_ECE522 CMOS IC Technologies Lectures. Karti Mayaram/part2.pdf
725.08 KB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_01.pdf
1.4 MB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_02.pdf
473.17 KB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_03.pdf
533.58 KB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_04.pdf
318.27 KB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_05.pdf
379.76 KB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_06.pdf
464.41 KB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_07.pdf
551.86 KB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_08.pdf
590.33 KB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_09.pdf
405.9 KB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_10.pdf
430.4 KB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_11.pdf
1.21 MB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_12.pdf
1.37 MB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_13.pdf
596.27 KB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_14.pdf
834.73 KB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_15.pdf
772.95 KB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_16.pdf
588.34 KB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_17.pdf
532.84 KB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_18.pdf
1.19 MB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_19.pdf
594.5 KB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_20.pdf
1.79 MB
EE130 Integrated Circuit Devices Lectures, Nathan Cheung/Lec_21.pdf
860.37 KB
From ASIC to SOCs.A practical Approach.Farzad Nekoogar, Faranak Nekoogar.chm
1.9 MB
High Speed CMOS Design Styles. 7 Autors from IBM.pdf
119.97 MB
IC Layout Basics.A Practical Guide.Christopher Saint, Judy Saint.pdf
37.65 MB
Introduction to CMOS OP-AMPS and Comparators.Roubik Gregorian.pdf
178.95 MB
The ART of Analog Layout.Alan Hastings/appa.pdf
44.65 KB
The ART of Analog Layout.Alan Hastings/appb.pdf
149.82 KB
The ART of Analog Layout.Alan Hastings/appc.pdf
210.89 KB
The ART of Analog Layout.Alan Hastings/appd.pdf
112.23 KB
The ART of Analog Layout.Alan Hastings/appe.pdf
20.49 KB
The ART of Analog Layout.Alan Hastings/ch01.pdf
1.74 MB
The ART of Analog Layout.Alan Hastings/ch02.pdf
1.61 MB
The ART of Analog Layout.Alan Hastings/ch03.pdf
2.08 MB
The ART of Analog Layout.Alan Hastings/ch04.pdf
1.79 MB
The ART of Analog Layout.Alan Hastings/ch05.pdf
1.74 MB
The ART of Analog Layout.Alan Hastings/ch06.pdf
1.06 MB
The ART of Analog Layout.Alan Hastings/ch07.pdf
3.03 MB
The ART of Analog Layout.Alan Hastings/ch08.pdf
2.34 MB
The ART of Analog Layout.Alan Hastings/ch09.pdf
2.67 MB
The ART of Analog Layout.Alan Hastings/ch10.pdf
918.89 KB
The ART of Analog Layout.Alan Hastings/ch11.pdf
1.99 MB
The ART of Analog Layout.Alan Hastings/ch12.pdf
2.38 MB
The ART of Analog Layout.Alan Hastings/ch13.pdf
2.42 MB
The ART of Analog Layout.Alan Hastings/ch14.pdf
1.39 MB
The ART of Analog Layout.Alan Hastings/contents.pdf
610.3 KB
The ART of Analog Layout.Alan Hastings/index.pdf
405.16 KB
The ART of Analog Layout.Alan Hastings/preface.pdf
59.09 KB
The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter00.pdf
587.72 KB
The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter01.pdf
4.86 MB
The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter02.pdf
3.74 MB
The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter03.pdf
3.05 MB
The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter04.pdf
3.43 MB
The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter05.pdf
4.37 MB
The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter06.pdf
2.47 MB
The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter07.pdf
10.21 MB
The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter08.pdf
13.95 MB
The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter09.pdf
2.86 MB
The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter10.pdf
3.78 MB
The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter11.pdf
8.66 MB
The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter12.pdf
3.84 MB
The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter13.pdf
8.13 MB
The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter14.pdf
11.14 MB
The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter15.pdf
11.26 MB
The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter16.pdf
9.56 MB
The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter17.pdf
2.41 MB
The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter18.pdf
2.85 MB
The Design of CMOS Radio-Frequency Integrated Cirquits.Thomas H.Lee/Chapter19.pdf
1.84 MB
The Designer's Guide to Verilog-AMS.Kundert, Zinke/ch1.pdf
230.17 KB
The Designer's Guide to Verilog-AMS.Kundert, Zinke/ch2.pdf
218.24 KB
The Designer's Guide to Verilog-AMS.Kundert, Zinke/ch3.pdf
214.61 KB
The Designer's Guide to Verilog-AMS.Kundert, Zinke/ch4.pdf
216.83 KB
The Designer's Guide to Verilog-AMS.Kundert, Zinke/ch5.pdf
228.76 KB
The Designer's Guide to Verilog-AMS.Kundert, Zinke/chA.pdf
218.46 KB
The Designer's Guide to Verilog-AMS.Kundert, Zinke/contents.pdf
204.96 KB
The Designer's Guide to Verilog-AMS.Kundert, Zinke/dg-vams1-errata.pdf
69.43 KB
The Designer's Guide to Verilog-AMS.Kundert, Zinke/index.pdf
220.22 KB
The Designer's Guide to Verilog-AMS.Kundert, Zinke/preface.pdf
203.48 KB
The Designer's Guide to Verilog-AMS.Kundert, Zinke/references.pdf
199.96 KB
Текстовый документ.txt
1.36 KB
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